Board and System Design

Astek provides complete turnkey solutions to companies developing hardware at the board or system level.  Astek has provided hardware solutions from single board FPGA prototype boards to complex systems requiring multiple boards, chassis and software development.  Astek has the hardware and software engineering expertise along with key manufacturing partners to deliver a complete hardware solution.  We have delivered solutions ranging from prototype platforms to complete production models. 

FPGA Design Examples

Astek has delivered a diverse set of designs ranging from Ethernet, Software Defined Radio, custom embedded processors, Image Processing,  storage and interface. We support design on Xilinx, Altera and Lattice, on single FPGAs or proprietary platforms. We stand ready to meet your needs!

FPGA DESIGNS

Ethernet DMA Controller
Features:  25MB/second transfer rate between external FIFOs and processor bus; simultaneous input/output operation; controls multiple external devices on processor bus; design converted from original gate-level schematics to synthesizable RTL for FPGA implementation; all external pinouts/timing unchanged; ASIC replaced with Xilinx Spartan-II FPGA.

Custom DSP Embedded Controller
Features:  100 Mhz, 16 bit fixed point pipelined dual harvard architecture with dual MACs. We first supplied a SystemC based simulation model for multiple customers. We refined, improved model till both our client and thier contractors were satisfied, then used that model to verify the RTL as well as provide a basis for Intruction Set Simulator. Design was produced in both FPGA and ASIC format.

ICE V6M Customization
Features:  Implemented a Software Defined Radio function including digital modulators,  demodulators, FEC and signal conditioning on the Inovative Computer Engineering (ICE) V6M platform. Deliveries included RTL, SystemVerilog based verification environment, JAVA based system interface. We supported product thru client lab debug, system integration and validation. At clients request, we also supported Xmidas integration.

Custom DSP Embedded Controller
Features:  100 Mhz, 16 bit fixed point pipelined dual harvard architecture with dual MACs. We first supplied a SystemC based simulation model for multiple customers. We refined, improved model till both our client and thier contractors were satisfied, then used that model to verify the RTL as well as provide a basis for Intruction Set Simulator. Design was produced in both FPGA and ASIC format.

Custom Digital Demodulator
Features:  Design supported advanced protocols such as DVBS-2.We implemented fixed point design using clients MatLab float point models using Altera Stratix4 based proprietary platform. Individual blocks include DDC, carrier-phase reconstruction, channel equalization, AGC, adaptive equalization, soft decision and hard decision decoding, FEC decoding. Design was supported thru clients lab debug, system validation and was fielded as a platform capability.

Programmable Timer Chip
Features:  RISC processor interface; multiple cascadable internal counters; programmable internal timer; design converted from original gate-level schematics to synthesizable RTL for FPGA implementation; all external pinouts/timing unchanged; ASIC replaced with Xilinx Virtex FPGA.

TELECOM - SONET/SDH OC-3/12
Features: Section, Line, and Path terminating interfaces; Astek has worked on Regenerators and Multiplexers, designing Framers, Pointer Processors, and overhead termination; single mode fiber interface (PHY) for DC-3 and DC-12.

TELECOM - ATM
Features:  ARM SAR, AAL-5 re-assembly, AAL-2 re-assembly; Astek has experience with ATM AAL-5 SAR and AAL-2 SAR design and test.

FIR/IIR DSP Test Platform
Implements multiple FIR/IIR DSP filter stages; 8-bit datapath; externally programmable filter coefficients; verifies proof of concept for new DSP algorithms; implemented in Xilinx Virtex FPGA.

Voice-over-IP Test Chip
Implements transmit and receive operations; controls data flow between transceivers, SDRAM, and PCI interfaces; 60 input channels; designed in VHDL; implemented in Xilinx 4000 series FPGA.

ASIC Design and Verification

Astek was founded to provide services to companies developing ASICs, in today's market there are fewer new ASIC designs, however Astek is still able to do such designs if your application requires it, we can also provide consulting to help you determine if an ASIC is the right solution, or if you should use an ASSP, FPGA or CPLD. With today's semiconductors reaching the extremes of density and speed, you may find a standard part is a lower-cost solution. On the other hand, Astek can help you combine digital and analog functions into a single part for unique applications that can cover the cost of NRE and require a very low per-unit incremental cost.

DIGITAL ASICS

PCI-X Dual Channel Ultra 320 SCSI Initiator/Target
Features: 64-bit 133 MHz master/slave PCI-X interface; dual 16-bit 320 MByte/sec Ultra 320 SCSI interfaces; 3 ARM 966 RISC processors; flash memory interface.  Multi-million gate design, First Pass Success.

PCI - Dual Channel ATA/ATAPI DMA Engine
Features: 32-bit, 66MHz, zero wait-state Master/Slave PCI interface;  Ultra ATA at up to 100 MB/sec per channel;  ATA sub-channel support;  EEPROM interface;  flash memory interface.

Hard Drive Disk Controller
Features: ANSI ATA-5/ATAPI host interface, ARM7TDMI RISC CPU, 5-way interleaved Reed-Solomon ECC block, high-speed SDRAM buffer controller, and Write Control Store RAM and Sequencer.

DATACOM - Ethernet/ IEEE-STD-802.3
Features:  10/100 NIC (Network Interface Card), Hub and Switch (layer 2); Astek Engineers have experience designing Ethernet NICs (Network Interface Card) that include 10BASE-T, 100BASE-TX, 10BASE-FL, and 100BASE-TX Network Interfaces for real-time systems and embedded processors; embedded 10/100 hubs and switches (Layer 2+).

Enclosure Services Processor
Features: 32-bit, 33 MHz, zero wait-state Master/Slave PCI interface with support for write and invalidate, read line, and read multiple commands; 80C32 microcontroller; LVD SCSI interface; SFF8067 interface; I2C interface; general purpose I/O.

Microcontroller ASIC
Features: Fully-synthesizable 8-bit microcontroller that is compatible with Motorola 68HC11 controllers. External peripherals include 3k RAM, Timer, Memory Expansion, External Chip Select, PWMs, Wired-OR Interrupts, RTC, and GPIO blocks. An external bus interface allows running a multiplexed or non-multiplexed external address/data bus.

DRAM Test Chip
Features:  Created a 1MB DRAM test chip for testing next generation DRAM storage materials.  Control signals were directly connected to external pins to facilitate testing and characterization of the new storage materials.  Special test structures added to memory array to allow characterization of individual memory cells.  Full custom layout performed and probe points added to top level for additional debug/characterization.

ANALOG ASICS

Precision Comparator
Features:  CMOS; accurate, programmable hysteresis; supply-independent, temperature-compensating bias current generator; wide common-mode input voltage range.

Analog Switch Chip
Features:  High-voltage, dielectrically-isolated process; CMOS, DMOS, and bipolar transistors; picoamp-level leakage currents; very low switch charge injection.

IP CORES

PCI-X Initiator/Target Core
Features:  64-bit; 33Mhz, 66Mhz, 100MHz, 133MHz operation; MSI support; up to 8 outstanding split transactions; power management support; low latency design.

PCI-X Mode 2 Initiator/Target Core
Features:  64-bit; 33Mhz, 66Mhz, 100MHz, 133MHz, and 266 MHz operation; MSI support; up to 8 outstanding; power management support; low latency design.

ATA-4/ATAPI Core
Features: Conforms to ANSI ATA-4/ATAPI specification and implements PIO Modes 0-4, DMA Modes 0-2, and Ultra DMA Modes 0-2 (Ultra DMA Mode 2 has a burst rate of 33 Mbyte/sec).

ATA-6/ATAPI Host Core
Features:  Conforms to ANSI ATA/ATAPI-6 specification for Host applications.  Supports PIO modes 0 through 4 and Ultra DMA modes 0 through 6(133MB/s).  Supports PACKET, queued, and overlapped command sets.  Supports 48-bit Addressing. Generic backend processor I/F.  Programmable command protocol.

ATA-6/ATAPI Device Core
Features:  Conforms to ANSI ATA/ATAPI-6 specification for Device applications.  Supports PIO modes 0 through 4 and Ultra DMA modes 0 through 6(133MB/s).  Supports PACKET, queued, and overlapped command sets.  Supports 48-bit Addressing. Generic backend processor I/F.

AHB Core Suite (Multi-Slave and Arbiter)
Features:  32, 64, 128 bits bus sizes; user-defined number of back ends; skewed or concurrent address/data phase outputs; split transfers enabled; busy pass through from back end; ARM AMBA Sped (rev 2.0) compliant.

Design Services

Astek offers a range of electronic design services, from direct staffing and manpower in Colorado Springs and the greater Rocky Mountain region, to managed project level contract services, calling upon our decades of experience in the high technology industries to deliver the right solution for your design needs.

• FPGA Design Examples
• ASIC Design and Verification
• Board and System Design