SCSI Ultra 320 ASIC Prototyping Vehicle
Features: 3.5 million gate design with three embedded ARM™ processors partitioned to multiple FPGAs prototyping platform.  The purpose was to verify functionality of SCSI and PCI-X protocol. Prototyping vehicle ran at approximately 1/4 speed of final chip design. RTL modification to update of prototyping vehicle hardware was under 4 hours (You could make a change at the RTL level and be verifying that change within 4 hours). Verification platform was cost effective to produce and several were sent to potential chip customers to help win design sockets. All major functional bugs found and first pass success achieved.

Two Gig Fibre Channel ASIC Prototyping Vehicle
Features: Single chip multi-million gate Fibre Channel 2G controller chip with embedded processors partitioned and targeted to a multiple FPGA (million gate FPGAs) verification platform. Both the Fibre and PCI-X verified at approximately 1/4 speed of final chip design. RTL modification to update of verification hardware was under 1/2 a day. Significant number of functional bugs found and fixed prior to tape out.

PCI-X / Dual Channel ATA/ATAPI Host Adapter
Features: Single chip multi-million gate ATA/ATAPI-5 Host controller with embedded ARM processor partitioned to multiple FPGA (million gate FPGAs) prototyping platform.  PCI-2.2 was verified at 33MHz.  The vehicle was able to reach PIO-2/Ultra-1 speeds on the ATA/ATAPI interface.  RTL modification to update of prototyping vehicle hardware was under 4 hours.  Hand modification of the FPGA(s) could accomplish small logic changes within 1/2 hour.  Significant number of critical functional bugs found.

Microcontroller ASIC Prototype
Features: 50k gate design including external 8-bit A/D to mimic a 68HC11 microcontroller. Prototype vehicle ran at full speed of final design. RTL modification to update of prototype hardware was under 1 hour. Significant number of functional bugs found and fixed prior to tape out.