Astek is looking for ASIC Digital Design Engineers interested
in designing and developing Verilog RTL code targeted towards a storage application.  This is initially a 3-month contract position with the potential of receiving additional extensions.  This position requires the individual to live or self-relocate to Colorado Springs, Co. 

Typical responsibilities include:
Reading digital functional specifications,
Breaking down functional specification to an Architecture,
Using VI or EMACs text editors to create design files,
Defining I/O and functional requirements for modules,
Writing Verilog RTL code for defined modules,
Writing functional test patterns to verify Verilog RTL code,
Creating and modifying Verilog Behavioral Level Modules (BLMs),
Writing and debugging UNIX and PERL scripts,
Utilizing Verilog and System Verilog Constructs,
Reading, understanding and adhering to project coding guidelines,
Using CVS as a Revision Control System for design files.

          REQUIREMENTS
BSEE or BSCE four year degree,
5 - 10 years experience as a Digital ASIC Design Engineer (beyond College),
ASIC design experience utilizing sub-nanometer CMOS digital libraries,
Working knowledge and experience with PERL and UNIX,
Experience with Verilog 2001 RTL and Open System Verilog 2003-2004,
Working knowledge of NCVERILOG simulator,
Willing to self relocate to Colorado Springs and work on-site,
Experience in storage protocols a plus.
Must be able to pass a general background check.

         REFERENCES
Must be able to supply three references with at least one
having been your direct superviser in a design role .

         SUMMARY
Astek is an Electronic Firm that offers products and ASIC/FPGA design services to its customer base.  Astek is located in Colorado Springs, Colorado at the base of Pikes Peak. We are looking for self-motivated team players with a positive "can do" attitude.