With modern FPGAs and CPLDs continually increasing density, speed and capability, designs that once would have required a metal-mask ASIC or standard-cell ASIC can be achieved on standard components at a fraction of the cost. What has not changed however, is the need for quality engineering digital logic design. NRE costs can spiral out of control if a project does not have a feasible architecture, and validation of the design requires more skill than simply applying random patterns. When designs can include millions of gates, embedded memories, SerDes for I/O, vendor supplied cores for buses like PCI-Express and Ethernet, and your own technology, the end of a project
Astek also offers FPGA design services. The service ranges from developing FPGA products, obsolete part replacements, to developing ASIC prototypes, which may include circuit card assemblies and test software. We have the infrastructure needed to provide a turnkey solution for customers requiring the development of an FPGA.
FPGA DESIGNS
Ethernet DMA Controller
Features: 25MB/second transfer rate between external FIFOs and processor bus; simultaneous input/output operation; controls multiple external devices on processor bus; design converted from original gate-level schematics to synthesizable RTL for FPGA implementation; all external pinouts/timing unchanged; ASIC replaced with Xilinx Spartan-II FPGA.
Programmable Timer Chip
Features: RISC processor interface; multiple cascadable internal counters; programmable internal timer; design converted from original gate-level schematics to synthesizable RTL for FPGA implementation; all external pinouts/timing unchanged; ASIC replaced with Xilinx Virtex FPGA.
TELECOM - SONET/SDH OC-3/12
Features: Section, Line, and Path terminating interfaces; Astek has worked on Regenerators and Multiplexers, designing Framers, Pointer Processors, and overhead termination; single mode fiber interface (PHY) for DC-3 and DC-12.
TELECOM - ATM
Features: ARM SAR, AAL-5 re-assembly, AAL-2 re-assembly; Astek has experience with ATM AAL-5 SAR and AAL-2 SAR design and test.
FIR/IIR DSP Test Platform
Implements multiple FIR/IIR DSP filter stages; 8-bit datapath; externally programmable filter coefficients; verifies proof of concept for new DSP algorithms; implemented in Xilinx Virtex FPGA.
Voice-over-IP Test Chip
Implements transmit and receive operations; controls data flow between transceivers, SDRAM, and PCI interfaces; 60 input channels; designed in VHDL; implemented in Xilinx 4000 series FPGA.
